As semiconductor integrated circuit chips become more multi-functional and highly integrated, the chips include more bonding pads (or terminal pads), and thus packages for the chips have more external terminals (or leads). When a conventional plastic package having leads along the perimeter of the package must accommodate a large number of electrical connection points, the footprint of the package increases. However, a goal in many electronic systems is to minimize an overall size of the systems. Thus, to accommodate a large number of pins without increasing the footprint of package, pin pitch (or lead pitch) of the package must decrease. However, a pin pitch of less that about 0.4 mm gives rise to many technical concerns. For example, trimming of a package having a pin pitch less than 0.4 mm requires expensive trimming tools, and the leads are prone to bending during handling of the package. In addition, surface-mounting of such packages demands a costly and complicated surface-mounting process due to a required critical alignment step.
Thus, to avoid technical problems associated with conventional fine-pitch packages, packages that have area array or leadless external terminals have been suggested. Among these packages are ball grid array packages, chip scale packages, Quad Flat-Pack No-Lead (QFN) packages, and Dual Flat-Pack No-Lead (DFN) packages. The semiconductor industry presently uses a number of chip scale packages. A micro ball grid array package (μBGA) and a bump chip carrier (BCC) are examples of the chip scale packages. The μBGA package includes a polyimide tape on which a conductive pattern is formed and employs a totally different manufacturing process from a conventional plastic packaging. The bump chip carrier package includes a substrate having grooves formed around a central portion of a top surface of a copper alloy plate and an electroplating layer formed in the groves. Accordingly, chip scale packages use specialized packaging materials and processes that increase package manufacturing costs.
FIG. 1A is a typical plastic encapsulated package 100 of the prior art (showing top 100A, bottom 100B, and side views 100C of the package). Specifically, the encapsulated package 100 is a QFN package. The QFN package 100 is a leadless package where electrical contact to a printed circuit board (PCB) is made by soldering lands on the bottom 100B surface of the package 100 to the PCB, instead of more traditional formed perimeter leads being soldered to the PCB.
FIG. 1B is a cross-sectional view of the prior art QFN package 100 in use and includes a copper land 101, a plurality of solder plating areas 103, a plurality of gold lead wires 105, and a down bond area 107. The copper land 101 frequently has a plating material 115 applied, such as silver, to facilitate gold or aluminum wire bonding (not shown). An integrated circuit die 109 is attached to the QFN package 100 with a suitable die attach material 113, such as a thermal epoxy. A mold compound 111 or other covering material is applied to finalize the QFN package 100.
Therefore, an integrated circuit package such as a QFN or DFN that uses conventional packaging materials and processes can only be accessed for electrical interconnection, for example, to a printed circuit board, by lower portions of the copper leadframe 101/plating area 103 (FIG. 1B) which are found only on the bottom surface of the package. Consequently, what is needed to provide for a higher density of integrated circuit packaging into a given printed circuit board footprint is a means of allowing the integrated circuit packages to be readily stacked, one atop another, or even side-by-side.